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High-speed Serial Buses in Embedded Systems
Feng Zhang
Verlag Springer-Verlag, 2020
ISBN 9789811518683 , 373 Seiten
Format PDF, OL
Kopierschutz Wasserzeichen
Preface
5
What This Book Is About?
5
Why the Serial Buses?
6
Who Is This Book For?
6
Outline of This Book
6
Contents
7
1 History and Development of Bus
13
1.1 Appearance and Definition of Bus
13
1.2 Progress of Bus in PC
15
1.2.1 ISA
16
1.2.2 PCI/PCI-X
17
1.2.3 PCIE
20
1.2.4 ATA/SATA—Used for Storage
22
1.3 Progress of Bus in Embedded System
24
1.3.1 The Emergence of Embedded Systems
24
1.3.2 PC104—The Embedded Version of ISA
26
1.3.3 Compact PCI—The Embedded Version of PCI
28
1.3.4 Compact PCI Express—The Embedded Version of PCI Express
31
1.3.5 SRIO—The Embedded System Interconnection
32
1.3.6 JESD204—Solving the ADC, DAC Data Transfer Problem
35
1.3.7 FC—A Combination of Channel I/O and Network I/O
36
1.3.8 VPX—An Integration Architecture of High-Speed Serial Bus
38
1.4 Analysis of the Three Evolutions of Bus
39
1.5 Common Attributes in High-Speed Serial Buses
43
1.6 The Development Trend of High-Speed Serial Bus in Embedded System
45
1.6.1 Speed Upgrades Constantly
46
1.6.2 Adoption of Multiple Signal Levels
46
1.6.3 Laser Communication and Its Miniaturization
47
1.6.4 Extended Reading—Laser Takes the Place of Microwave Communication [36]
49
References
51
2 High-Speed Data Transfer Based on SERDES
53
2.1 Brief Introduction to Serdes
53
2.2 LVDS—Physical Layer of Serdes
54
2.3 Data Transfer Based on Serdes Primitive Embedded in FPGA
57
2.3.1 FPGA Supports LVDS Level
57
2.3.2 FPGA Embeds-in OSERDESE2/ISERDESE2 Primitives
58
2.3.3 Analysis of the Transfer Rate of Serdes
60
2.4 Implementation of Serdes Transfer Function in FPGA
61
2.4.1 OSERDESE2 Configuration at the Transmitter in FPGA
61
2.4.2 ISERDESE2 Design at the Receiver in FPGA
74
2.4.3 Experiment Result of Serdes Communication
82
2.5 Extended Reading—Optimization Scheme for Multi-channel Communication Based on Serdes
83
2.5.1 Clock Region Optimization
84
2.5.2 MAXSKEW
85
2.5.3 Offset
87
2.5.4 IDELAY2 Primitives to Adjust the Delay
89
2.5.5 A Self-Adaptive Delay Adjustment Scheme Based on Idelay2 Primitive
92
2.6 Brief Summary
93
2.7 Extended Reading—A New Rising Star: Xilinx and Its FPGA
94
References
95
3 ADC, DAC Data Transmission Based on JESD204 Protocol
97
3.1 Introduction to JESD204 Protocol
97
3.2 Detailed Analysis of JESD204 Specification
102
3.2.1 JESD204 Physical Layer Analysis
102
3.2.2 Frame Padding
104
3.2.3 8B/10B
105
3.2.4 Scrambling/De-scrambling
108
3.2.5 Analysis of JESD204 Protocol Receiver State Machine
109
3.3 Implementation of JESD204 Protocol Based on GTX Embedded in FPGA
112
3.3.1 Feasibility Analysis—Physical Layer Electrical Characteristics Compatibility
113
3.3.2 GTX Structure Analysis
113
3.3.3 Build the FPGA Project for JESD204 IP Core Based on GTX
121
3.3.4 Analysis of Some Technical Points of JESD204 Protocol
135
3.4 Summary
140
References
141
4 SRIO: The Embedded System Interconnection
143
4.1 SRIO—Dedicated for the Embedded System Interconnection
143
4.1.1 Embedded Bus and PC Bus Applications Went Separate Ways
143
4.1.2 SRIO Technology Dedicated for Embedded System Interconnection
145
4.1.3 SRIO Versus PCIE Versus Ethernet Versus Others
147
4.2 SRIO Protocol Analysis
149
4.2.1 SRIO Protocol Hierarchical Structure
149
4.2.2 SRIO Physical Layer Specification
152
4.2.3 Packet and Operation Types
155
4.2.4 Lane Synchronization
158
4.2.5 Lane Encoding
158
4.2.6 Configuration Space
161
4.3 Point to Point SRIO Communication Based on FPGA
161
4.3.1 Create the SRIO Project
163
4.3.2 SRIO Project Structure Analysis [7]
174
4.3.3 Analysis and Realization of Key Technology of SRIO Point-to-Point Communication
176
4.3.4 SRIO P2P Communication Function Test
179
4.4 The Implementation of Communication Function of SRIO Switch Fabric
180
4.4.1 Overview of the SRIO Switch Fabric
180
4.4.2 Brief Introduction on SRIO Switch Chip 80HCPS1616 [8, 9]
181
4.4.3 The Configuration of SRIO Switch Chip 80HCPS1616
183
4.4.4 I2C Configuration Interface for 80HCPS1616
190
4.4.5 Maintenance Frame Configuration for SRIO Switch Chip
192
4.4.6 Communication Function Test of SRIO Switch Fabric
198
4.5 Summary
199
References
201
5 Transmission Technology Based on Aurora Protocol
202
5.1 Aurora Bus Overview
202
5.2 Aurora Bus Protocol Analysis
203
5.2.1 Aurora Bus Communication Model
203
5.2.2 Electrical Characteristics of Aurora Physical Layer
204
5.2.3 Aurora Data Frame Structure
206
5.2.4 Aurora Lane Synchronization
208
5.3 Implementation of Aurora Point-to-Point Data Transmisstion Between FPGAs
212
5.3.1 Establish Aurora Bus Testing Project
212
5.3.2 Analysis of Aurora Bus Protocol Files and Interfaces
218
5.3.3 Aurora Bus Frame Mode and Streaming Mode
220
5.3.4 Aurora Bus Communication Performance Analysis and Test
225
5.4 Summary
228
References
228
6 High Speed Data Storage Technology Based on SATA
229
6.1 Various Modes of High-Speed Data Storage Technology and the Involved Buses
230
6.1.1 Data Storage Mode Based on ATA Bus Standard
230
6.1.2 High Speed Data Storage Mode Based on SCSI Bus Standard
232
6.1.3 High Speed Data Storage Mode Based on SAS/SATA Bus Standard
234
6.1.4 Extended Reading—High Speed Data Storage Mode Based on NandFlash Arrays
237
6.1.5 Extended Reading—High Speed Data Storage Mode Based on eMMCs and Its Array
240
6.1.6 Comparison and Analysis of Multiple Storage Implementations
241
6.2 SATA Protocol Analysis
242
6.2.1 Architecture
242
6.2.2 OOB Process
243
6.2.3 Primitives and Frame Information Structures
245
6.2.4 Encode Scheme
250
6.3 Implementation of SATA IP Core in FPGA
250
6.3.1 Brief Introduction to ML50x Evaluation Platforms [15]
251
6.3.2 Brief Introduction to Virtex-5 FPGA GTX [16]
251
6.3.3 GTX Configurations to Comply with SATA Protocol
254
6.3.4 OOB Communication of SATA Protocol
262
6.3.5 Implementation of 8B/10B, CRC and Scrambling
265
6.3.6 Implementation of Analysis on Application Layer of SATA Protocol
267
6.3.7 Implementation of Application Layer
273
6.3.8 SATA Protocol IP CoreTest
274
6.4 Summary
276
6.5 Extended Reading—DNA-Based Biology Storage Technology
277
Appendix 1: SATA CRC32 Implementation in VHDL
283
Appendix 2: SATA Scrambling Implementation in VHDL
290
References
296
7 Compact PCI Express
298
7.1 From ISA to PCI to PCIE
298
7.2 Compact PCIE—Embedded Version of PCIE
304
7.3 Classification of Functional Modules in CPCIE
306
7.4 CPCIE Connectors and Signals Definition
308
7.4.1 Connectors
308
7.4.2 Definition of Signals
310
7.5 System Design Considerations
321
7.5.1 Functional Labels of Boards
321
7.5.2 Power Supply Requirements
323
7.5.3 Clock Design
325
7.6 Summary
325
References
326
8 VPX Architecture
327
8.1 Brief Introduction to VPX and Its Origin VME
327
8.2 Analysis on VPX Protocol Families
331
8.3 Signals and Interconnect
335
8.3.1 VME32 Signals
335
8.3.2 VPX Signals
337
8.3.3 Pin Mappings Between Backplane and Plug-in Modules
337
8.4 System Design Consideration
337
8.4.1 Logical Topology
337
8.4.2 Connectors Selection
340
8.4.3 Backplane Keying
341
8.4.4 Power Design
343
8.5 Summary
348
References
349
9 Implementation and Application of FC Protocol
350
9.1 Brief Introduction to FC
350
9.1.1 FC Appears from Big Data, Clouds and SAN
350
9.1.2 Advantages of FC
352
9.1.3 FC Roadmap
353
9.1.4 Applications of FC to Airborne Avionics
354
9.2 Analysis of FC Specification
355
9.2.1 FC Topology
355
9.2.2 Hierarchical-Layered Structure
357
9.2.3 FC Protocol Families
359
9.2.4 Frame Structure and Coding Scheme
359
9.2.5 Classes of Service
363
9.2.6 Interface Forms
368
9.3 Analysis on Realization of FC Protocols
368
9.3.1 Realization Scheme Based on IP of Xilinx
369
9.3.2 Realization Method Based on ASICs
370
9.4 Summary
372
References
373