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Dependable Computing - Design and Assessment

Dependable Computing - Design and Assessment

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Nithin M. Nakka

 

Verlag Wiley-IEEE Press, 2024

ISBN 9781119743446 , 848 Seiten

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Kopierschutz DRM

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Dependable Computing - Design and Assessment


 

Dependable Computing Covering dependability from software and hardware perspectives Dependable Computing: Design and Assessment looks at both the software and hardware aspects of dependability. This book:
  • Provides an in-depth examination of dependability/fault tolerance topics
  • Describes dependability taxonomy, and briefly contrasts classical techniques with their modern counterparts or extensions
  • Walks up the system stack from the hardware logic via operating systems up to software applications with respect to how they are hardened for dependability
  • Describes the use of measurement-based analysis of computing systems
  • Illustrates technology through real-life applications
  • Discusses security attacks and unique dependability requirements for emerging applications, e.g., smart electric power grids and cloud computing
  • Finally, using critical societal applications such as autonomous vehicles, large-scale clouds, and engineering solutions for healthcare, the book illustrates the emerging challenges faced in making artificial intelligence (AI) and its applications dependable and trustworthy.
This book is suitable for those studying in the fields of computer engineering and computer science. Professionals who are working within the new reality to ensure dependable computing will find helpful information to support their efforts. With the support of practical case studies and use cases from both academia and real-world deployments, the book provides a journey of developments that include the impact of artificial intelligence and machine learning on this ever-growing field. This book offers a single compendium that spans the myriad areas in which dependability has been applied, providing theoretical concepts and applied knowledge with content that will excite a beginner, and rigor that will satisfy an expert. Accompanying the book is an online repository of problem sets and solutions, as well as slides for instructors, that span the chapters of the book.

Ravishankar K. Iyer is George and Ann Fisher Distinguished Professor of Engineering at the University of Illinois Urbana-Champaign, USA. He holds joint appointments in the Departments of Electrical & Computer Engineering and Computer Science as well as the Coordinated Science Laboratory (CSL), the National Center for Supercomputing Applications (NCSA), and the Carl R. Woese Institute for Genomic Biology. The winner of numerous awards and honors, he was the founding chief scientist of the Information Trust Institute at UIUC-a campus-wide research center addressing security, reliability, and safety issues in critical infrastructures. Zbigniew T. Kalbarczyk is a Research Professor in the Department of Electrical & Computer Engineering and the Coordinated Science Laboratory of the University of Illinois Urbana-Champaign, USA. He is a member of the IEEE, the IEEE Computer Society, and IFIP Working Group 10.4 on Dependable Computing and Fault Tolerance. Dr. Kalbarczyk's research interests are in the design and validation of reliable and secure computing systems. His current work explores emerging computing technologies, machine learning-based methods for early detection of security attacks, analysis of data on failures and security attacks in large computing systems, and more. Nithin M. Nakka received his B. Tech (hons.) degree from the Indian Institute of Technology, Kharagpur, India, and his M.S. and Ph.D. degrees from the University of Illinois Urbana-Champaign, USA. He is a Technical Leader at Cisco Systems and has worked on most layers of the networking stack, from network data-plane hardware, including layer-2 and layer-3 (control plane), network controllers, and network fabric monitoring. His areas of research interest include systems reliability, network telemetry, and hardware-implemented fault tolerance.